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Design Linked Incentive Scheme For Semiconductors

Design Linked Incentive Scheme For Semiconductors

Context: 

This editorial is based on the news “The need to overhaul a semiconductor scheme which was published in The Hindu. This article highlights the need for revamp and significance of semiconductor Design Linked Incentive scheme, as the mid-term appraisal of the semiconductor Design-Linked Incentive (DLI) scheme is due soon.

Relevancy for Prelims: Design Linked Incentive Scheme, PLI Scheme 2.0 For IT HardwareSemiconductor Manufacturing, and India’s First Semiconductor Memory Chip

Relevancy for Mains: Design Linked Incentive Scheme for Semiconductors- Need, Challenges and Way Forward.

About the Design Linked Incentive Scheme:

  • Financial Assistance Scheme: Design Linked Incentive Scheme offers financial incentives, design infrastructure support across various stages of development and deployment of semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design.
  • Aim: To cultivate semiconductor design capabilities in India, with the understanding that home-grown IP will organically evolve as local talent fosters the creation of indigenous companies over time. 
  • Design Linked Incentive SchemeNodal Agency: The Centre for Development of Advanced Computing, a scientific society operating under MeitY.
  • Need to Revamp: Since its announcement, the DLI scheme has approved only seven start-ups, markedly short of its target of supporting 100 over five years. 
    • This presents an opportunity for policymakers to appraise and revamp the scheme.
  • Significance: It will boost India’s status as a semiconductor powerhouse. 
    • However, resources are limited. Therefore, priorities for industrial policy should ensure investments. 
      • India’s $10 billion Semicon India Program has had mixed results, at best. 

Issues with the Design Linked Incentive Scheme

  • Limit on Incentives: The Design Linked Incentive Scheme mandates that beneficiary start-ups maintain their domestic status for at least three years after receiving incentives, and for this they cannot raise more than 50% of their requisite capital via foreign direct investment. 
  • High Cost for Semiconductor design Startups: The funding landscape for chip start-ups in India continues to be challenging despite promising IP and business potential. 
  • Impact on Long-term Access: The relatively modest incentives under the Design Linked Incentive Scheme (capped at ₹15 Crore for Product DLI and ₹30 Crore for Deployment Linked Incentive, per application) would not make for a worthwhile trade-off for start-ups standing to lose out on access to crucial long-term funding. 
  • Low Participation: The Design Linked Incentive Scheme has witnessed lackluster results and low participation.
  • Ineffective Nodal Agency: Concerns are raised about the nodal agency’s role, posing potential conflicts of interest.

Goals of India’s Semiconductor Strategy

  • Reduce dependency on Imports: Particularly from China, and especially in strategic and emerging sectors, ranging from defense applications to Artificial Intelligence development. 
  • To build Supply Chain Resilience: By integrating into the semiconductor global value chain (GVC). 
  • To double down on India’s Comparative Advantage: India already plays host to the design houses of every major global semiconductor industry player and Indian chip design engineers are an indispensable part of the semiconductor GVC.

Way Forward to the Design Linked Incentive Scheme

  • Equity Financing: Any shortfall in investment for Design Linked Incentive Scheme beneficiary start-ups could be bridged by equity financing bringing in foreign funds.
  • Delinking of Ownership: Delinking of ownership from the development of semiconductor design and adopting more start-up-friendly investment guidelines is required. This would also boost their financial stability and provide them global exposure.
  • Revision of the Scheme: The scheme needs to be revised to focus on the broader objective of facilitating design capabilities for a wide array of chips within the country, so long as the entity engaging in the design development process is registered in India. 
  • Enhancement of the Financial Outlay: To support the policy shift.
  • New and EffectiveImplementing Agency: Karnataka’s Semiconductor Fabless Accelerator Lab (SFAL), with its specific partnerships with the Indian Electronics and Semiconductor Association, EDA vendors, IP, and testing companies, could be an appropriate implementing agency for DLI.
  • Cultivating Indigenous Capabilities: To boost the sector in India for long-term success.
Also Read: India EU Semiconductor Pact

 

Mains Question: Discuss the significance of the semiconductor industry to the Indian economy. Do you believe India’s semiconductor industry has reached its full potential? Explain the reasons for the same. Also, highlight the government’s recent initiatives to strengthen India’s semiconductor ecosystem. (250 Words, 15 Marks)

 

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UPSC Mains Previous Year Papers UPSC Test Series 2024

 

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 Final Result – CIVIL SERVICES EXAMINATION, 2023.   Udaan-Prelims Wallah ( Static ) booklets 2024 released both in english and hindi : Download from Here!     Download UPSC Mains 2023 Question Papers PDF  Free Initiative links -1) Download Prahaar 3.0 for Mains Current Affairs PDF both in English and Hindi 2) Daily Main Answer Writing  , 3) Daily Current Affairs , Editorial Analysis and quiz ,  4) PDF Downloads  UPSC Prelims 2023 Trend Analysis cut-off and answer key

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UDAAN PRELIMS WALLAH
Comprehensive coverage with a concise format
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Quick Revise Now !
UDAAN PRELIMS WALLAH
Comprehensive coverage with a concise format
Integration of PYQ within the booklet
Designed as per recent trends of Prelims questions
हिंदी में भी उपलब्ध

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